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ATM Layer Processor Project Example

Background

Our Customer required a pluggable daughter board which provided an OC-12 interface on the network side to a UTOPIA Interface to the Customers Baseboard. The daughter board was controlled from an MPC860 running VXWorks.

A2E's responsibilities included the

  • Hardware Design and Manufacture of the daughter board
  • Software Drivers in VxWorks for Status and Configuration
  • FPGA Code to implement the required rate adaption and cell processing
The FPGA functionality was implemented in a low cost Altera Cyclone FPGA (EP1C12). This functionality could have been provided with a 3rd party chip set - ATM Cell processor ASIC plus external memory. However the FPGA solution has several advantages:
  • Considerably lower cost
  • Small PCB footprint and much simplified PCB design compared to the multichip ASIC plus external memory
  • Simpler to program.
  • Easily expandable (i.e. by selecting a larger density part with the same footprint ). In this case the FIFO buffering could be increased by replacing the EP1C6 device with EP1C12 Cyclone FPGAs.

FPGA Overview

The ATM layer processor implements the following blocks:
  • L2 Utopia master controller for the OC12 PHY and base board interfaces
  • Cell processing - PVC routing based on cell VPI/VCI/PHY_ADDRESS mapping
  • Cell insertion/extraction - DS1.2 function
  • ATM layer loopback
  • Processor interface
  • Glue logic

OC12-Uplink Board FPGA

ATM Layer Processor FPGA Overview



Utopia Interfaces

Utopia L2 master controllers are used for both the OC12 and base board utopia buses. The base board controllers support multiple PHY addresses with standard address polling, 16-bit data width and 50MHz clock frequency. This frequency supports the full cell throughput of the OC12 interface. The polling cycle supports the full cell throughput of the OC12 interface (622Mbps bi-directional).The OC12 Masters are also 16 bit 50MHz but support a single address. The base board utopia bus supports 16 PHY addresses allocated to the customer PHYs. The OC12 utopia bus only addresses the single OC12 PHY. The cells will be buffered in both directions to allow for the latencies incurred by the utopia polling mechanism. In the downstream direction 16-cell FIFOs are implemented for each of the 16-channels in the baseboard Tx-Utopia interface. In the upstream direction a single 4-cell FIFO is implemented in the OC12 Tx-Utopia interface.

Cell Processor

The cell processor modifies the cell header and route based on the cells VPI, VCI and PHY_ADDRESS header fields to establish multiple PVCs between the OC12 PHY and base board PHY. The configured PVCs operate separately for both the OC12 PHY and the baseboard PHYs. The mapping is configured by software over the microprocessor interface. In the down stream direction the cells VPI and VCI fields are used to map the cell to a baseboard PHY. The cells VPI, VCI and PHY_ADDRESS are translated and the cell forwarded. In the up stream direction the cells VPI, VCI and PHY_ADDRESS fields are used to translate the cells VPI and VCI. In this direction the destination is always the OC12 PHY. For following ranges are supported for each field: VPI range: 0-32d VCI range: 0-255d Up to 16 PVCs per PHY giving a total of 256 active PVCs

Cell Insertion and Extraction

Cells can be inserted and removed by software using the Microprocessor Interface.

Microprocessor Interface

A 16bit wide microprocessor interface is provided to allow a MPC860 host to configure and manage the board.

Test Interface and Modes

Test features include loop back, pass through and statistics

Misc Glue Logic

The FPGA also provides miscellaneous logic functions such as address decoding, power on reset gating and retiming of the microprocessor bus control signals for the OC12 PHY.

Project Examples

ATM Layer FPGA

ARC Angel 4

Reactec HAVmeter


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